Peripheral Features

I2C Controller Feature (0x601)

The I2C Controller Feature provides a bridge to manage devices on an I2C bus. This is useful for interfacing to MIPI video devices that provide an I2C port for management.

The controller can manage multiple I2C devices on the same bus if they have unique addresses.

I2C Controller Declaration

Feature ID

0x601

Version

0x001

(0.1)

Pointer Count

2

Bootstrap ID

0x60100102

(Max pointers)

Pointer 0

Reg Block

I2C Peripheral Block

Pointer 1

String

Description

I2C Controller Pointers

I2C Controller Registers

Register Offset 0 — Status

I2C Status Register

Done

Holding

Unused

Rate

Max

TxLevel

RxLevel
I2C Rx FIFO Register Fields

Field

Access

msb

len

Description

Done

RO

31

1

'0' indicates Controller is Idle

Holding

RO

30

1

'1' indicates Controller is holding the bus

Rate

RO

23

4

0x1=100kbps, 0x4=400kbps, 0x8=1Mbps

MaxLevel

RO

19

4

Maximum FIFO level

TxLevel

RO

15

8

Current entries in Tx FIFO

RxLevel

RO

7

8

Current entries in Rx FIFO

Register Offset 4 — Config

I2C Config Register

Unused

Reset
I2C Config Fields

Field

Access

msb

len

Description

Reset

RWSC

0

1

Resets I2C controller and FIFOs, self-clearing

Register Offset 8 — Tx Data FIFO

I2C Tx FIFO Register Field Map

Unused

Stop

Hold

Ack

Data
I2C Tx FIFO Register Fields

Field

Access

msb

len

Description

Stop

WO

10

1

'1' adds a Stop condition after the data byte

Hold

WO

9

1

'1' holds the bus for the next byte

Ack

WO

8

1

Ack value to set after data byte

Data

WO

7

8

Data byte to transfer

Register Offset 0xC — Rx Data FIFO

I2C Rx FIFO Register Field Map

Unused

Ack

Data
I2C Rx FIFO Register Fields

Field

Access

msb

len

Description

Ack

RO-AoW

8

1

Ack bit captured after the byte

Data

RO-AoW

7

8

Byte value captured from the I2C bus

Pointer 1 — Port Description

Pointer to a null-terminated string describing the function of this I2C Controller (e.g. corresponding MIPI port).

SPI Controller Feature (0x602)

The SPI Controller Feature provides a bridge to manage devices on a SPI bus. Useful for updating SPI Flash memories containing FPGA and microcontroller firmware.

SPI Controller

Feature ID

0x602

Version

0x001

(0.1)

Pointer Count

4

Bootstrap ID

0x60200104

(Max pointers)

Pointer 0

Reg 32

Config

Pointer 1

Reg 32

Control

Pointer 2

Reg 32

SPI Tx Buffer

Pointer 3

Reg 32

SPI Rx Buffer

TBD pointer descriptions

UART Controller Feature (0x603)

UART Controller

Feature ID

0x603

Version

0x001

(0.1)

Pointer Count

4

Bootstrap ID

0x60300104

(Max pointers)

Pointer 0

Reg 32

UART Configuration

Pointer 1

Reg 32

UART Status

Pointer 2

Reg 32

UART Tx Buffer

Pointer 3

Reg 32

UART Rx Buffer

TBD pointer descriptions

SMI (MDIO/MDC) Controller Feature (0x604)

The SMI Controller Feature offers pointers to SMI (MDIO/MDC) controller registers, typically connected to Ethernet PHYs.

SMI Controller

Feature ID

0x604

Version

0x001

(0.1)

Pointer Count

4

Bootstrap ID

0x60400104

(Max pointers)

Pointer 0

Reg 32

SMI Configuration

Pointer 1

Reg 32

SMI Status

Pointer 2

Reg 32

SMI Tx Buffer

Pointer 3

Reg 32

SMI Rx Buffer

TBD pointer descriptions

CAN Controller Feature (0x605)

TBD pointer table

TBD pointer descriptions

PWM Port Feature (0x606)

TBD pointer table

TBD pointer descriptions

GPIO Port Feature (0x607)

EEVideo devices may implement register-driven GPIO pins.

GPIO Controller

Feature ID

0x607

Version

0x001

(0.1)

Pointer Count

4

Bootstrap ID

0x60700104

(Max pointers)

Pointer 0

Reg 32

GPIO Port Config

Pointer 1

Reg 32

GPIO Direction

Pointer 2

Reg 32

GPIO In

Pointer 3

Reg 32

GPIO Out

TBD pointer descriptions